StarFive launches Dubhe-100 RISC-V core for servers: 15/GHz SPECint2006 score and 15-stage pipeline

Chinese semiconductor company StarFive has unveiled the Dubhe-100, a new high-performance 64-bit RISC-V processor core designed for servers, high-performance computing (HPC), and other demanding workloads. The core is fully compliant with the RVA23 specification, the latest standard for RISC-V application-class processors.

The Dubhe-100 achieves a SPECint2006 score of 15 per GHz and a Dhrystone v2.2 score of 10.0 per MHz in legal mode. It is built around a deep out-of-order execution engine with a 15-stage pipeline and 6-wide superscalar instruction dispatch. The core supports the Vector (V) and Vector Crypto (V Crypto) extensions, as well as the Advanced Interrupt Architecture (AIA) version 1.0.

Key features include multi-core cache coherence support, instruction fusion for improved throughput, and standard RISC-V Hardware Performance Monitors (HPM) that allow microarchitecture-level analysis and performance tuning. For memory protection, the core offers configurable Physical Memory Protection (PMP) and Physical Memory Attributes (PMA) with support for 16, 32, or 64 protection regions, each with a minimum granularity of 4096 bytes. The core also supports the Svpbmt extension for page-based memory attributes.

Debug and trace capabilities are standard-compliant: the integrated debug module follows the RISC-V Debug Specification, and the trace module interface adheres to the RISC-V Trace Specification. Power management features are also included.

The ISA is based on RV64GCBVH, which bundles the base integer, multiplication, atomic, floating-point, compressed, vector, and hypervisor extensions. The Dubhe-100 is positioned as a direct competitor to existing high-end RISC-V cores from companies like SiFive and Esperanto, targeting markets traditionally dominated by Arm and x86 architectures. StarFive has not yet disclosed pricing, licensing terms, or availability dates for the core. The company plans to release further technical documentation and performance benchmarks in the coming months.