Rapidus targets 49 chips per panel by 2030 — TSMC fights back with 14-reticle CoWoS in 2028

Rapidus has laid out its advanced packaging roadmap at the 2026 OCP APAC Summit, targeting eight-reticle-size interposers (6,640 mm²) on 600×600 mm panels by around 2030. The plan was presented by Rozalia Beica, CTO of Rapidus Design Solutions, and details a gradual increase in interposer size: from four reticles (3,320 mm²) to six (4,980 mm²), and finally to eight.

The 600×600 mm panel format is the centerpiece of the strategy, as it offers a dramatic yield advantage over traditional wafer-based processing. Beica illustrated the difference with a simple comparison: an eight-reticle interposer yields just four units on a standard 300 mm wafer, nine on a 300×300 mm panel, 36 on a 510×515 mm panel, and 49 on a 600×600 mm panel. This jump in output is critical for high-performance computing and AI accelerators that require large, complex interposers.

Rapidus's rival TSMC is pursuing a different path with its CoWoS interposer roadmap. TSMC plans to reach 5.5 reticles in 2026, 9.5 reticles in 2027, and 14 reticles by 2028. While TSMC's approach relies on scaling up on 300 mm wafers, Rapidus is betting entirely on panel-level processing. The two companies are thus taking fundamentally different manufacturing routes to serve the same market of large AI and HPC chips.

The 600 mm panel effort is already in progress. Rapidus has demonstrated the format and is working with Lam Research's Kallisto electroplating system to develop 2.xD packaging with redistribution layers formed on 600 mm glass carriers. In late 2025, Rapidus reported producing the first test samples using this equipment, marking a step toward commercial panel-level packaging. The company's roadmap suggests that by 2030, it could offer a competitive alternative to TSMC's wafer-based CoWoS, particularly for customers needing very large interposers in high volume.